AMD Vitis™ High-Level Synthesis (HLS) optimization traditionally demands significant expertise and time spent in micro-architecture design and pragma retuning. This session examines how AI-assisted workflows are reshaping the design process.

We'll explore how the Model Context Protocol (MCP) closes the knowledge gap, and how Skills (best practices that boost LLM results) encapsulate proven methodology to close the expertise gap. Through case studies based on actual designs, attendees will learn practical techniques to accelerate FPGA design and reduce time-to-performance.

Suitable for both new and experienced HLS designers.

The agenda for this webinar includes:

• The traditional Vitis HLS development flow and its challenges
• AI-Assisted Vitis HLS: building the foundation
• Skills for Vitis HLS: concepts and case studies

Register now to join us live!